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a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 rev 1.0 /aug. 2010 1 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash 16gb nand flash H27UAG8T2B *58b7d520-e522* b26798/177.179.157.212/2010-08-06 17:39
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 2 document title 16gbit (2048 m x 8 bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. feb. 25. 2010 preliminary 0.1 draft version release mar. 08. 2010 preliminary 1.0 final version release spec. change : twhr ( before : 80ns min / after : 100ns min) aug. 06. 2010 release *58b7d520-e522* b26798/177.179.157.212/2010-08-06 17:39
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 3 1. summary description multilevel cell technology supply voltage - 3.3v device : vcc = 2.7 v ~ 3.6 v vcc = 2.7 v ~ 3.6 v organization - page size : 8,640 bytes(8,192+448 bytes) - block size : 256 pages(2m+112k bytes) - plane size : 512 blocks page read time - random access: 200 ? (max.) - sequential access : 25 ? (min.) write time - page program : 1600 ? (typ.) - block erase : 2.5 ? (typ.) operating current - read - program - erase - standby hardware data protection - program/erase locked during power transitions endurance - 3,000 p/e cycles (with 24 bit/ 1,024byte ecc) data retention - 10 years package - tsop (12x20), 48pin - wafer (bare die) unique id for copyright protection *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 4 1. summary description the H27UAG8T2B is a single 3.3v 16gbit nand flash memory. the device contains 2 planes in a single die. each plane is made up of the 512 blocks. each block consists of 256 programmable pages. each page contains 8,640 bytes. the pages are subdivided into an 8,192-bytes main data storage area with a spare 448-byte district. page program operation can be performed in typical 1,600us, and a single block can be erased in typical 2.5ms. on- chip control logic unit automates erase and program operatio ns to maximize cycle endurance. e/w endurance is stipu- lated at 3,000 cycles when using relevant ecc and error management. the H27UAG8T2B is a best solution for applications requiring large nonvolatile storage memory. 1.1. product list table 1 part number organization vcc range package H27UAG8T2B x8 2.7v ~ 3.6v 48 - tsop1 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 5 1.2. packaging information gg 0 figure 1. 48-tsop1 contact, x8 device 0 figure 1-1. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline symbol millimeters min typ max a1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 nc nc nc nc nc nc r/b re ce nc nc vcc vss nc nc cle ale we wp nc nc nc nc nc nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc nc vc cq vssq nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 12 13 37 36 25 48 1 24 nand flash tsop1 (x8) ' $ ',( $ h % / . ( ( & &3 $ *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 6 48-tsop1 - 48-lead plastic thin small outl ine, 12 x 20mm, package mechanical data pin diagram 0 figure 2. pin diagram pin names e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 symbol millimeters min typ max vcc vss wp# cle ale re# we# ce# i/o0~i/o7 r/b# 870 vvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 7 1.3. pin description pin name description i/o0-i/ o7 data inputs/outputs the i/o pins are used to command latch cycle, addr ess input cycle, and data in-out cycles during read / write operations. the i/o pins float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the i/o inputs inside the command register on the rising edge of write enable (we#). ale address latch enable this input activates the latching of the i/o inputs inside the address register on the rising edge of write enable (we#). ce# chip enable this input controls the selection of the device. when the device is bu sy, ce# low does not deselect the memory. the device goes into stand-by mode when ce# goes high during 10us in ready state. the ce# signal is ignored when device is in busy stat e, and will not enter standby mode even if the ce# goes high. we# write enable this input acts as clock to latch command, addre ss and data. the i/o inputs are latched on the rise edge of we#. re# read enable the re# input is the serial data-out control, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re# which also increments the internal co lumn address counter by one. wp# write protect the wp# pin, when low, provides a hardware protec tion against undesired write operations. hardware write protection is activated when the write protect pi n is low. in this condition modify operation do not start and the content of the memory is not altered. write protect pin is not latched by write enable to ensure the protection even during the power up phases. r/b# ready / busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations. (read, write, and erase). vss ground nc no connected i/o7~i/o0 data input / outputs cle command latch enable ale address latch enable ce# chip enable re# read enable r/b# ready / busy we# write enable wp# write protect vcc power supply vss ground nc no connection *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 8 notes: a 0.1uf capacitor should be connected between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be suffic ient to carry the currents required during program and erase operations. 1.4. block diagram 0 figure 3. block diagram x decoder address register ale cle ce# we# re# wp# command interface logic program/erase controller hv generation y decoder address register command register io buffer & latch x d e c o d e r nand flash memory array 1 device = (8,192 + 448) bytes x 256pages x 1024 blocks = 17,694,720 kbits data register & sense amp column decoder vcc vss global data buffer output driver a14-a31 a0-a13 i/o<7:0> 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 9 1.5. g array organization 0 figure 4. array organization 1.6. addressing notes: ggg 1. l must be set to low. ggg 2. the device ignores any additional address input cycle than required. ggg 3. the address consists of column address (a0~a13) , page address (a14 ~ a21), plane address (a22), and ggggggg block address (a23 ~ the last address). bus cycle i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 1 st cycle a0 a1 a2 a3 a4 a5 a6 a7 2 nd cycle a8 a9 a10 a11 a12 a13 l (1) l (1) 3 rd cycle a14 a15 a16 a17 a18 a19 a20 a21 4 th cycle a22 a23 a24 a25 a26 a27 a28 a29 5 th cycle a30 a31 l (1) l (1) l (1) l (1) l (1) l (1) 8,640 bytes 8,640 bytes 8,192 8,192 8,192 8,192 448 448 448 448 1 block 1 block plane 0 plane 1 512 blocks/plane 1024 blocks/device i/o 0 i/o 7 1 page = (8,192 + 488 bytes) 1 block = (8,192 + 488) bytes x 256 pages = (2m + 112k) bytes 1 device = (8,192 + 488) bytes x 256 pages x 1024 block = 17,694,720 kbits *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 10 1.7. command set notes: 1. random data input/output mu st be performed in a selected page. 2. any command between 11h and 81h is prohibited except 70h, 78h, and ffh. 3. multi plane random data-out must be used after mult i plane read operations (multi plane page read, multi plane cache read and mult i plane read for copy back). 4. do not change plane address orde r when using all multi plane operations. 5. all cache operation (cache program, cache read) is available only within a block. 6. interleave operation between two chips are allowed. multi plan e read status (78h) can be used to check each chip status. it is prohibited to use read status command (70h) in interleaved operation. function 1st cycle number of address cycles data input cycles 2nd cycle number of address cycles data input cycles 3rd cycle accept- able com- mand during busy page read 00h 5 - 30h - - - no read for copy-back 00h 5 - 35h - - - no random data output 1) 05h 2 - e0h - - - no single/multi plane cache read 5) 31h - - - - - - no single/multi plane cache read end 5) 3fh - - - - - - no read id 90h 1 - - - - - no read status register 70h - - - - - - yes page pgm (start) / cache pgm 5) (end) 80h 5 yes 10h - - - no random data input 1) 85h 2 yes - - - - no copy-back pgm 85h 5 option 10h - - - no cache pgm (start) 5) 80h 5 yes 15h - - - no block erase 60h 3 - d0h - - - no reset ffh - - - - - yes multi plane page read 60h 3 - 60h 3 - 30h no multi plane cache read start 5) 60h 3 - 60h 3 - 30h/ 33h no multi plane read for copy-back 60h 3 - 60h 3 - 35h no multi plane block erase 60h 3 - 60h 3 - d0h no multi plane data output 1) 3) 00h 5 - 05h 2 - e0h no multi plane read status regis- ter 78h 3 - - - - - yes multi plane page pgm / multi plane cache pgm (end) 80h 5 yes 11h~81h 2) 5yes10hno multi plane copy-back pgm 85h 5 option 11h~81h 2) 5option10h no multi plane cache pgm (start) 5) 80h 5 yes 11h~81h 2) 5yes15hno user otp entry command 04h 19h no unique id read entry command 02h 19h no unique id pgm entry command 84h 97h 08h no read id2 entry command 30h 65h no *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 11 caution: 1. any undefined command inputs are prohibited except for above command set. 2. multi plane page read, multi plan e cache read, and multi plane read for co py-back must be used after multi plane programmed page, multi plane cache program, and multi plane copy-back program. 1.8. mode selection notes: ggg 1. x can be vil or vih. h = logi c level high. l = logic level low. ggg 2. wp# should be biased to cmos high or cmos low for stand-by mode. ggg 3. g we# and re# during read busy must be keep on high to prevent unplanned command/address/data input or to ggggggg avert unintended data out. in this time, only reset, read status, and multi plane read status can be inputted to ggggggg the g device. cle ale ce# we# re# wp# mode hl l h x read mode command input l h l h x address input ( 5 cycles ) hl l h h write mode command input l h 1) l h h address input ( 5 cycles ) l l l h h data input l l 1) l h x sequential read and data output xx x h 3) h 3) x during read (busy) x x 1) xxxh during program (busy) x x x x x h during erase (busy) x x x x x l write protect xx h x x 0v/vcc 2) stand-by *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 12 1.9. bad bloc k management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping . any block where the 1st byte in the spare area of either the 1st or the last page does not contain ffh is a bad bloc k. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to re cognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in flow chart 1( bad block management flow chart ). the 1st block, which is placed on 00h bl ock address, is guaranteed to be a valid block at the time of shipment. 0 flow chart 1. bad block management flow chart notes: ggg 1. do not try to erase the detected bad blocks, because the bad block information will be lost. ggg 2. do not perform program and erase operation in invalid block, it is impossible to guarantee the input data gggggg and to ensure that the function is normal. start block no = 0 read ffh check column 8192 of the first page last block end entry bad block fail fail pass yes block no. = block no. + 1 pass no read ffh check col. 8192 of the last page 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 13 1.10. bad block replacement this device may have the invalid blocks when shipped from fa ctory. an invalid block is one that contains one or more bad bits. over the lifetime of the device additional bad blocks may develop. in this case, the block has to be replaced by copying the data to a valid block. th ese additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. the failure of a page program operation does not affect the data in other pages in the same block. bad block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. refer to table 2 ( block failure ) and figure 5 ( block replacement ) for the recommended procedure to follow if an error occurs during an operation. table 2. block failure 0 figure 5. block replacement notes: 1. an error occurs on nth page of the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. nth page of block a which is in controller buffer memory is copied into nth page of block b. 4. bad block table should be updated to prevent from erasing or programming block a. operation recommended procedure erase block replacement program block replacement read ecc block a block b data data failure ffh ffh buffer memory controller 1 page st 1 page st nth page nth page (2) (3) 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 14 2. electrical characteristics 2.1. valid blocks notes: 1. the 1st block is guaranteed to be a valid block at the time of shipment. 2. this single device has a maximum of 25 invalid blocks. 3. invalid blocks are one that contains one or more bad bits. the device may contain bad blocks upon shipment. 2.2. absolute maximum rating notes: 1. except for the rating "operating temperature ra nge", stresses above those li sted in the table "absolute maximum ratings" may cause permanent damage to the device. these are stre ss ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the hynix sure program and other relevant quality documents. 2. minimum voltage may undershoot to -2v during transition and for less th an 20ns during transitions. symbol min typ max unit valid block number n vb 999 1024 blocks symbol parameter value unit min t a ambient operating temperature (commercial temperature range) 0 to 70 c ambient operating temperature (extended temperature range) -25 to 85 c ambient operating temperature (industrial temperature range) -40 to 85 c t bias temperature under bias -50 to 125 c t stg storage temperature -65 to 150 c v io input or output voltage -0.6 to 4.6 v v cc supply voltage -0.6 to 4.6 v *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 15 2.3. dc and operating characteristics 2.4. ac test conditions notes: ggg 1. these parameters are verified device characterization and are not 100% tested. parameter symbol test conditions H27UAG8T2B unit 3.3v min typ max power on reset current i cc0 ffh command input after power on -- 50per device a operating current read i cc1 t rc = t rc (min), ce#=v il , i out =0 a --50 a program i cc2 ---50 a erase i cc3 ---50 a stand-by current (ttl) i cc4 ce#=v ih , wp#=0v/ v cc -- 1 a stand-by current (cmos) i cc5 ce#=vcc-0.2, wp#=0v/v cc -1050 input leakage current i li v in =0 to v cc (max) -- 10 output leakage current i lo v out =0 to v cc(max) -- 10 input high voltage v ih - vccx0.8 - vcc+0.3 v input low voltage v il - -0.3 - 0.2x vcc v output high voltage v oh i oh =-200 2.4 - - v output low voltage v ol i ol =2.1 a --0.4 v output low current (r/b#) i ol (r/ b#) v ol =0.4v 810 - a parameter value 2.7v vcc g 3.6v input pulse levels 0 g v to v cc input rise and fall times 5 g? input and output timing levels vcc /2 output load (2.7v-3.6v) 1 ttl gate and cl=50 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 16 2.5. g pin capacitance (t a =25c s f=1.0 ) 2.6. program/ read / erase characteristics notes: 1. typical value is measured at v cc =3.3v, t a =25 . not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v -10?? c i/o input/output capacitance v in = 0v -10?? parameter symbol min typ max unit program (following 10h) t prog - 1600 5 000 cache program (following 15h) t cbsyw - - 5000 multi plane program / multi plane cache program / multi plane copy-back program (following 11h) t dbsy - 3 5 cache read / multi plane cache read (following 31h/3fh) t cbsyr - 3 200 block erase / multi plane block erase t bers - 2.5 10 ? number of partial program cycles in the same page nop - - 1 cycles *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 17 2.7. ac timing characteristics parameter symbol 3.3v unit min max cle setup time t cls 12 ? cle hold time t clh 5 ? ce# setup time t cs 20 ? ce# hold time t ch 5 ? we# pulse width t wp 12 ? ale setup time t als 12 ? ale hold time t alh 5 ? data setup time t ds 12 ? data hold time t dh 5 ? write cycle time t wc 25 ? we# high hold time t wh 10 ? data transfer from cell to register t r 200 ale to re# delay t ar 10 ? cle to re# delay t clr 10 ? ready to re# low t rr 25 ? re# pulse width t rp 12 ? we# high to busy t wb 100 ? read cycle time t rc 25 ? re# access time t rea 20 ? re# high to output high z t rhz 100 ? ce# high to output high z t chz 50 ? re# high to output hold t rhoh 15 ? re# low to output hold t rloh 5 ? re# or ce# high to output hold t coh 15 ? re# high hold time t reh 10 ? ce# low to re# low t cr 10 ? we# high to re# low t whr 100 ? re# high to we# low t rhw 100 ? output high z to re# low t ir 0 ? address to data loading time t adl 100 ? *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 18 notes: 1. if reset command (ffh) is written at ready state, the device goes into busy for maximum 5us. 2. program / erase enable op eration: wp# high to we# high. program / erase disable operation: wp# low to we# high. 3. the transition of the corresponding control pins must occur only while we# is held low. 4. t adl is the time from the we# rising edge of final addr ess cycle to the we# rising edge of first data cycle. 2.8. status register coding notes: 1. i/o0: this bit is only valid for program an d erase operations. during cache program operations, this bit is only valid when i/o5 is set to one. 2. i/o1: this bit is only valid for cache program operations. this bit is not valid until after the second 15h command or the 10h command has been transferred in a cache program sequence. when cache program is not supported, this bit is not used. 3. i/o5: if set to one, then th ere is no array operation in progress. if cleared to zero, then there is a command being processed (i/o6 is cleared to zero) or an array oper ation in progress. when overlapped interleaved operations or cache commands are not supported, this bit is not used. 4. g i/o6: if set to one, then the device or inte rleaved address is ready for another command and g all other bits in the status value are valid. if cleared to zero, then the last command issued is not yet complete and status register bits<5:0> are invalid value. when cache operations are in use, then this bit indicates whether another command can be accepted, and i/o5 g indicates whether the last operation is complete. device resetting time (read/program/erase) t rst 20/30/500 write protection time t ww 100 ? i/o page program block erase read cache read cache program coding 70h/ 78h 0 pass/ fail pass/ fail n/a n/a pass/ fail n page pass : '0' fail : '1' 1 n/a n/a n/a n/a pass/ fail n-1 page pass : '0' fail : '1' 2n/an/an/an/an/a '0' 3n/an/an/an/an/a '0' 4n/an/an/an/an/a '0' 5 n/a n/a n/a ready / busy ready / busy ready / busy busy : '0' ready : '1' 6 ready / busy ready / busy ready / busy ready / busy ready / busy data cache ready / busy : '0' ready : '1' 7 write protect write protect write protect write protect write protect protected : '0' not protected : n 1 n *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 19 2.9. device identifier coding 2.10. read id data table 2.10.1. 3 rd byte of device identifier description parameter symbol device identifier byte description 1 st manufacturer code 2 nd device identifier 3 rd internal chip number, cell type , number of simultaneously pro- grammed pages, interleaved program, write cache. 4 th page size, block size, redundant area size 5 th plane number, ecc level 6 th technology (design rule), edo, interface part number voltage bus width manufacture code device code 3 rd 4 th 5 th 6 th H27UAG8T2B 3.3v x8 adh d5h 94h 9ah 74h 42h 3 rd cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 internal chip number 1 2 4 reserved 0 0 1 1 0 1 0 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 1 1 0 1 0 1 number of simultaneously programmed pages 1 2 4 8 0 0 1 1 0 1 0 1 interleaved program between multiple dice supported not supported 0 1 write cache not supported supported 0 1 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 20 2.10.2. 4 th byte of device identifier description 2.10.3. 5 th byte of device identifier description 4 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 page size (without spare area) 2kb 4kb 8kb reserved 0 0 1 1 0 1 0 1 block size (without spare area) 128kb 256kb 512kb 768kb 1mb 2mb reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 redundant area size 128b 224b 448b reserved reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 5 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 plane number 1 2 4 8 0 0 1 1 0 1 0 1 ecc level 1bit/512bytes 2bit/512bytes 4bit/512bytes 8bit/512bytes 16bit/512bytes 24bit/2048bytes 24bit/1024bytes reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 reserved 0 0 0 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 21 2.10.4. 6 th byte of device identifier description 6 th cycle description i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 i/o 0 nand technology 48nm 41nm 32nm reserved reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 edo support not support support 0 1 nand interface sdr ddr 0 1 reserved 0 0 0 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 22 3. g timing diagram bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. 3.1. command latc h cycle timings 0 figure 6. command latch timings note: all commands except reset, read st atus, and multi plane read status are issued to command register on the rising edge of we#, when cle is high, ce# and ale is lo w, and device is not busy state cl s cs wp command cle ce# we# ale i/ox dh ds als clh ch : dont care tt t t t t t t alh t 870 vvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 23 3.2. address latch cycle timings 0 figure 7. address latch timings 3.3. input data la tch cycle timings 0 figure 8. input data cycle timings tcls tcs twc tals tals tals tals tals talh talh talh talh talh twc twc twc twp twp twh twp twp twh twh twh tds col.add1 cle ce we ale i/ox col.add2 row add1 row add2 row add3 tds tds tds tds tdh tdh tdh tdh tdh : dont care wc clh ch wp wh din 1 din final dh dh dh ds ds ds wp wp cle ale ce# i/ox we# als din 0 t t t t t t t t t t t t t t : dont care 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 24 note: data input cycle is accepted to data register on the rising edge of we#, when cle and ce# and ale are low, and device is not busy state. 3.4. data output cycle timings (cle=l, we#=h, ale=l, wp#=h) 0 figure 9. data output cycle timings notes: 1. transition is measured +/-200m v from steady state voltage with load. this parameter is sampled and not 100% tested. ( t chz , t rhz ) 2. t rloh is valid when frequency is higher than 33mhz. t rhoh starts to be valid when frequency is lower than 33mhz. 3.5. data output cycle timings (edo type, cle=l, we#=h, ale=l) 0 figure 10. data output cycle timings (edo) notes: 1. transition is measured +/-200m v from steady state voltage with load. this parameter is sampled and not 100% tested. ( t chz , t rhz ) reh rea rc rr chz rhz rhoh dout dout ce# re# i/ox r/b# dout rea rhz rea t t t t t t t t t t rr chz rhz rhoh dout ce# re# i/ox r/b# rea dout rloh rea rp reh rc t t t t t t t t t t : dont care cr t 58b7d520-e522 iy]vxxxyxyvywxwtwtw]gxaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 25 2. t rloh is valid when frequency is higher than 33mhz. t rhoh starts to be valid when frequency is lower than 33mhz. 3.6. read status cycle timings 0 figure 11. read status timings 3.7. multi plane read status timings 0 figure 12. multi plane read status timings cle ce# re# i/ox we# 70h status output cls t clh t cs t clr t ch t cr t chz t rhz t rhoh t wp t whr t ds t dh t ir t rea t : dont care t cls t clh t cs t wp t ch t cr t chz t coh t whr t alh t ar t rea t rhz t rhoh t ds t dh t alh t als wc t wp t wh t : dont care c le c e# w e# a le r e# / ox 78h row.add1 row.add2 row.add3 status 58b7d520-e522 iy]vxxxyxyvywxwtwtw]gxaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 26 3.8. page read operation timings (read one page) 0 figure 13. page read operation timings 3.9. page read operation timings (intercepted by ce#) 0 figure 14. page read operation timings ce# cle ale we# re# i/ox 00h col. add1 col. add2 row. add1 row. add2 row. add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t rhz dout m ce# cle ale we# re# i/ox 00h col. add1 col. add2 row. add1 row. add2 row. add3 30h dout n dout n+1 dout n+2 r/b# t ar t rc t r t wb t rr t wc : dont care t clr t chz t coh t cs t ch t cls t clh 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 27 3.10. page read operation timings with ce# don't care 0 figure 15. page read operation timings with ce# don't care note: random data output is available within a page. 3.11. random data output timings 0 figure 16. random data output timings note: random data output is available within a page. *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 28 3.12. multi plane page read operatio n with random data output timings 0 figure 17. multi plane page read oper ation timings with random data output notes: ggg 1. multi plane page addresses are required to be the same. ggg 2. multi plane random data-out must be used after multi plane read operations. ggg 3. multi plane page read must be used after multi plane programmed page, multi plane cache program, gggggg and multi plane co py-back program. *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 29 3.13. cache read operation timings 0 figure 18. cache read operation timings notes: ggg 1. the column address will be reset to 0 by the 31h/3fh command input. ggg 2. cache read operation is av ailable only within a block. *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 30 3.14. multi plane cache read operation timings 0 figure 19. multi plane cach e read operation timings notes: ggg 1. the column address will be reset to 0 by the 31h/3fh command input. 2. cache read operation is available only within a block. 3. make sure to terminate the operation with 3fh command. if the page read operation is completed, issue ffh reset before next operation. 4. multi plane page addresses are required to be the same. 5. multi plane cache read must be used after multi plane programmed page, multi plane cache program, and multi plane copy-back program *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 31 3.15. read id operation timings 0 figure 20. read id operation timings 3.16. page program operation timings 0 figure 21. page program operation timings note: t adl is the time from the we# rising edge of final addres s cycle to the we# rising edge of first data cycle. device code 3rd cyc. 4th cyc. 90h ce# cle we# ale re# i/ox 00h adh ar whr rea 5th cyc. 6th cyc. maker code t t t 58b7d520-e522 iy]vxxxyxyvywxwtwtw]gxaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 32 3.17. page program operation timings with ce# don't care 0 figure 22. page program operation timings with ce# don't care note: t adl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle. 3.18. random data input timings 0 figure 24. random data input timings notes: 1. t adl is the time from the we# rising edge of final addr ess cycle to the we# rising edge of first data cycle. 2. random data input can be performed in a page. 80h col. add1 col. add1 row. add1 row. add2 row. add3 din n din n+1 din m din p din p+1 din r 10h don ? t care ce# cle ale we# i/ox t cs t ch t wp ce# we# *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 33 3.19. multi plane page program operation timings 0 figure 25. multi plane page program operation timing notes: 1. any command between 11h and 81h is prohibited except 70h, 78h and ffh 2. t adl is the time from the we# rising edge of final addres s cycle to the we# rising edge of first data cycle. 3. multi plane page addresse s are required to be the same. 80h col. add1 col. add2 row add1 row add2 row add3 d in n d in n+1 d in m 11h a a 81h col. add1 col. add2 row add1 row add2 row add3 d in n d in n+1 d in m 10h 70h status ce# cle ale we# i/ox ce# cle ale we# re# i/ox r/b# a0 ~ a13 : valid a14 ~ a21 valid (page m) a22 : fixed low a23 ~ a31 : valid (block j) a0 ~ a13 : valid a14 ~ a21 valid (page m) a22 : fixed high a23 ~ a31 : valid (block k) r/b# t wc t wb t dbsy t wb t prog t adl t whr io 0 = 0, pass io 0 = 1, fail t wc *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 34 3.20. copy-back program operation timings with random date input 0 figure 26. copyback program operatio n timing with random data input notes: 1. copy back operation is allowe d only within the same memory plane. 3.21. cache program operation timings 0 figure 27. cache program operation timings note: t prog = program time for the last page + program time for the (las t -1)th page - (command input cycle time + address input cycle time + last page data loading time *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 35 3.22. multi plane cache pr ogram operation timings 0 figure 28. multi plane cach e program operation timings notes: 1. t prog = program time for the last page + program time for the (last -1)th page - (command input cycle time + address input cycle time + last page data loading time) 2. make sure to terminate the operation with 80h-10h - command sequence. if the op eration is terminated, issue ffh reset before next operation. 3. selected page address except a22 within two blocks must be same. 80h col. add1 col. add2 row add1 row add2 row add3 d in n d in m 11h a ce# cle ale we# i/ox a0 ~ a13 : valid a14 ~ a21 valid (page m) a22 : fixed low a23 ~ a31 : valid (block j) r/b# t wc t wb t dbsy 81h col. add1 col. add2 row add1 row add2 row add3 d in n d in m 15h t adl t wc t adl t cbsyw a0 ~ a13 : valid a14 ~ a21 valid (page m) a22 : fixed high a23 ~ a31 : valid (block k) 80h col. add1 col. add2 row add1 row add2 row add3 d in n d in m 11h ce# cle ale we# i/ox a0 ~ a13 : valid a14 ~ a21 valid (page m+n) a22 : fixed low a23 ~ a31 : valid (block j) r/b# t wc t wb t dbsy 81h col. add1 col. add2 row add1 row add2 row add3 d in n d in m 10h t adl t wc t adl t prog a0 ~ a13 : valid a14 ~ a21 valid (page m+n) a22 : fixed high a23 ~ a31 : valid (block k) a *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 36 3.23. block erase operation timings 0 figure 29. block erase operation timings 3.24. multi plane erase operation timings 0 figure 30. multi plane erase operation timings 60h row add1 row add2 row add3 60h ce# cle ale we# i/ox a14 ~ a21 fixed low a22 : fixed low a23 ~ a31 : valid (block n) re# t wc t bers 70h row add1 row add2 row add3 d0h status a14 ~ a21 fixed low a22 : fixed high a23 ~ a31 : valid (block m) io 0 = 0, pass io 0 = 1, fail don ? t care r/b# t wb t whr *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 37 3.25. reset timings 0 figure 31. reset timings ffh t rst ce# cle we# i/ox r/b# t wb 58b7d520-e522 iy]vxxxyxyvywxwtwtw]gxaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 38 4. device operation 4.1. page read this operation is initialized by 00h-30h to the command regi ster along with followed by five address input cycles. the 8,640 bytes of data within the selected page are transferred to the data registers in less than 200 (t r ). the system controller may detect the completion of this data transfer 200 (t r ) by analyzing the output of r/b# pin. once the data in a page is loaded into the data registers, they may be read out in 25 ? cycle time by sequentially pulsing re#. the repetitive high to low transitions of the re# clock make the device output the data starting from the selected col- umn address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out- put command. the column address of next data, which is go ing to be out, may be changed to the address, which fol- lows random data output command. random data output can be operated multiple times, regardless of how many times it is done in a page. 0 figure 32. page read random data output random data output operation changes the column address fr om which data is being read in the page register. ran- dom data output only is issued in ready state. refer to figure 33. 0 figure 33. random data output cle ale ce# i/ox we# r/b# re# 00h address (5 cycle) 30h data output (serial access) t r i/ox r/b# re# 00h data t r output address (5 cycle) 30h data output 05h address (2 cycle) e0h 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 39 4.2. cache read (available only within a block) to improve page read throughput, cache read operation is used within a block. first step is same as normal page read, issuing a page read sequence (00-30h). after random access (r/b# returns to hi gh), 31h command is latched into the command register. data is being transferred from the data re gister to the cache register. while cache register data is outputted, next page is transferred from memory cell to data register. r/b# wi ll stay low during present page random accessing and previous page transferring to cache register. because it is not necessary to output a whole page data before issuing another 31h command, if serial da ta output time exceeds random access time (t r ), the random access time can be hidden. the subsequent pages are issued a dditional 31h commands. to terminate cache read, 3fh com- mand should be issued. this co mmand transfer data from data register to the cache register without issuing next page read. during the cache read operation, device doesn't allow any other command except cache read command (31h), read status (70h, 78h), read (00h), and reset (ffh). to ca rry out other operations after cache operation, cache read must be ended by 3fh command or issu e reset (ffh) before next operation. 0 figure 34. cache read 4.3. multi plane page read multi plane page read is an extension of page read, for a single plane with 8640byte page registers. since the device is equipped with two memory planes, activating the two sets of 8640byte page resisters enables a random read of two pages. multi plane page read is initiated by repeating comma nd 60h followed by three addr ess cycles twice. in this case, only same page can be selected from each plane. after read confirm command (30h) the 17280bytes of data wi thin the selected two pages are transferred to the data registers in less than 200 (t r ). the system controller can detect the completion of data transfer (t r ) by monitoring the output of r/b# pin. once the data is loaded into the data registers, the data output of first plan e can be read out by issuing command 00h with five address cycles, command 05h with two column a ddress and finally e0h. the data output of second plane can be read out using the identical comma nd sequences. the restrictions for mu lti plane page read are shown in fig- ure 35. multi plane page read must be used in the block which has been programmed with multi plane page program. 30h 31h d0 ... dn 31h d0 ... dn 3fh d0 ... dn cle we# re# i/ox r/b# as defined for read t r t cbsyr column 0 t cbsyr column 0 t cbsyr column 0 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 40 0 figure 35. multi plane page read 4.4. multi plane cache read (available only within a block) the device supports multi plane cache read, which enab les high read throughput by reading two pages in parallel. figure 36 shows the command se quence for the multi plane cache read operation. both confirm commands, 30h and 33h, are valid for the first page read sequence. 0 figure 36. multi plane cache read 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address : valid address (3 cycle) 60h 30h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid 00h address (5 cycle) address (2 cycle) 05h e0h data output t r 60h address (3 cycle) 60h address (3 cycle) 33h 31h 00h address (5 cycle) 05h address (2 cycle) e0h data output t cbsyr a b a 00h address (5 cycle) 05h address (2 cycle) eoh column address : fixed low page address : page m plane address : fixed low block address : block j column address : valid data output i/ox r/b# i/ox r/b# i/ox r/b# b column address : fixed low page address : page m plane address : fixed high block address : block k column address : valid *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 41 notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. multi plane cache read is avai lable only within a block per plane. 4. selected page address except for a22 within two blocks must be same. 5. the operation has to be terminated with "3fh" command. 4.5. read id the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. six read cycles sequentially output the manufacturer code (adh), and the device code and 3rd, 4th, 5th, 6th cycle id, respectively. the command register re mains in read id mode until further commands are issued to it. figure 37 shows the operatio n sequence, while 2.10 read id data tables explain the byte meaning. 0 figure 37. read id 4.6. g read status register the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is completed successfully. after writing read status (70h) or multi plane read status (78h) command to the command register, a read cycle outputs the content of the status register to the i/o pins only if ce# and re# are low, whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections ev en when r/b# pins are common-wired. refer to 2.8. sta- tus register codings for specific status register defini tions and figure 38, figure 39 for read status. the com- mand register remains in read status mo de until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. 0 figure 38. read status 90h cle we# ale re# i/ox 00h adh d7h 74h 42h 9ah whr 94h t 70h status cle we# re# i/ox 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 42 0 figure 39. multi plane read status cle ale we# re# i/ox 78h row.add1 row.add3 row.add2 status 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 43 4.7. page program the device is programmed as a page unit. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 times. the program addressing should be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 8640bytes of data may be loaded into th e data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. th e serial data-loading period begins by inputting the serial data input com- mand (80h), followed by the five cycle address inputs an d then serial data. the bytes other than those to be pro- grammed do not need to be loaded. the device supports ra ndom data input in a page. the column address of next data, which will be entered, may be changed to the address which follows ra ndom data input command (85h). ran- dom data input may be operated multiple times, regardless of how many times it is done in a page. the page program confirm command (10h) initiates the programming process. wr iting 10h alone without previo usly entering the serial data will not initiate the programming process. the intern al write state controller auto matically executes the algo- rithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of a progra m cycle by monitoring the r/b# output, or the status bit (i/o 6) of the status register. only the read status co mmand and reset command are valid while programming is in progress. the write status bit (i/o 0) is valid, when all internal operations are complete (status bit i/o 6 = high). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mo de until another valid command is written to the com- mand register. figure 40 and figure 41 details the sequence. 0 figure 40. page program 0 figure 41. random data input 80h address 5 cycle data input status 70h 10h cle prog t i/o 0 = 0 program pass i/o 0 = 1 program fail ce# ale we# re# i/ox r/b# i/ox r/b# column address 80h address (5 cycle) address (2 cycle) data input 85h data input 70h status 10h prog t 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 44 4.8. multi plane program device supports multiple plane progra m. it is possible to program in pa rallel 2 pages, one per each plane. a multiple plane program cycle consists of a double serial da ta loading period in which up to 17,280bytes of data may be loaded into the data register, followed by a non-volati le programming period where the loaded data is programmed into the appropriate cell. the serial data loading period be gins by inputting the serial data input command (80h), fol- lowed by the five cycle address inputs and then serial data for the 1st page. address for this page must be within first plane (a<22>=0). the data of first page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program op eration. the dummy page program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (t dbsy ). once it has become ready again, 81h command must be issued, followed by second page address (5 cycles) and its serial data input. address for this page must be within second plane (a<22>=1). the data of seco nd page other than those to be programmed do not need to be loaded. program confirm command (10h) makes parallel programming of both pages start. user can check oper- ation status by r/b# pin or read status register command, as if it were a normal page program; status register com- mand is also available during dummy busy time (t dbsy ). in case of fail in first plane or second plane page program, fail bit of status register will be set: pass/fail status of ea ch plane can be checked by multi plane read status. figure 42 details the sequence. 0 figure 42. multi plane page program notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. selected page address except for a22 within two blocks must be same. 4. any command between 11h and 81h is prohibited except 70h/78h and ffh. 5. read status command can be 70h or 78h. 4.9. cache program (available only within a block) cache program is an extension of the standard page program, which is executed with 8,640 bytes cache registers and same bytes data register. after the serial data input comman d (80h) is loaded to the command register, followed by 5 cycles of address, a full or partial page of data is latc hed into the cache register, an d then the cache write command (15h) is loaded to the command register. after that sequence, the data in the cach e register is transferred into the data register for cell programming. at this time, the device remains in busy state. after all data of the cache register is transferred into the data register, the device goes to the re ady state to load the next data into the cache register by issuing another cache program command sequence (80h-15h). there are some restrictions for cache program operation. 1. the cache program command is available only within a block. 2. user must give address and data after 80h command. the busy time of first sequence equals th e time it takes to transfer the data of cache register to the data register. cell programming of the data of data register and loading of th e next data into the cache register is consequently pro- cessed as a pipeline method. on the second and cascading se quence, transfer from the cach e register to the data reg- ister is held off until cell programming of current data register contents has been done. read status command (70h) may be issued to find out when the cache register is ready by polling the cache-busy sta- 80h address (5 cycle) 11h t dbsy data input a 81h address (5 cycle) 10h t prog data input i/ox r/b# 70h status 1 plane address st 2 plane address nd a i/ox r/b# 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 45 tus bit (i/o 6). in addition, the status bit (i/o 5) can be used to determine when the cell programming of the current data register contents is complete. pass/fail status of only the previous page (i/o 1) is available upon the return to ready state. the last page of the target programming sequence must be programmed with actual ?page program? command (10h). if single plane cache program begins, single plane sequence should be used until single plane cache program is ended. pass/fail status is available in two steps. i/o 1 returns with the status of the pr evious page upon ready or i/o6 status bit changing to "1", and later i/o 0 with the status of current page upon true ready (returning from internal program- ming) or i/o 5 status bit changing to "1". i/o 1 may be re ad together when i/o 0 is checked. refer to 2.8. status register coding and figure 43 for more details. 0g figure 43. cache program 80h address (5 cycle) 15h t cbsyw data input a 80h address (5 cycle) 15h t cbsyw data input b i/ox r/b# 80h address (5 cycle) 10h t prog data input i/ox r/b# 70h status a b i/ox r/b# r/b# pin data cache ready /bysy (i/o6) i/o 1 => i/o 0 => invalid invalid page1 invalid page1 page2 page n-2 invalid invalid invalid page n-1 page n data cache ready /bysy (i/o5) 70h sr out 70h sr out 80h-add-data-15h 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 80h-add-data-15h 70h sr out 70h sr out page 1 page 2 page n-1 page n page 1 page 2 page n-1 page n during both i/o6 and i/o5 return to high, the pass/fail for previous page and current page can be shown through i/o1 and i/o0 concurrently. prog t cbsyw t cbsyw t cbsyw t pass / fail status for each page programmed by the cache program operation can be detected by the read status operation. i/o 0 : pass / fail of the current page program operation. i/o 1 : pass / fail of the previous page program operation. the pass / fail status on i/o 0 and i/o 1 are valid under the following conditions. status on i/o 0 : ready / busy is ready state. the ready/ busy is output on i/o 5 by read status operation or r/b pin after the 10h command. status on i/o 1 : data cache ready / busy is ready state. the data cache ready / busy is output on i/o 6 by read status operation or r/b pin after the 15h command. 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 46 4.10. g multi plane cache program (available only within a block) the device supports multi plane cache pr ogram, which enables high program throughput by programming two pages. the serial data-loading period begins by inputting the serial data input command (80h), followed by the five cycle address inputs and then serial data for the first page. addre ss for this page must be with in first plane (a<22>=0). the data of first page other than those to be programmed do not need to be loaded. the device supports random data input exactly like page program operation. the dummy pa ge program confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tdbsy). once it has beco me ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. addres s for this page must be within second plane (a<22>=1). the data of second page other than those to be programme d do not need to be loaded. cache program confirm command (15h) makes parallel programming of both pages start. and last page inputs program confirm command (10h). the last page of the target programming sequence mu st be programmed with actual page program command (10h). if the operation is terminated, issue ffh reset before next operation. if multiplane cache program begins, multiplane sequence should be used until multiplane cache program is ended. figure 44 shows the command sequen ce for multi plane cache program operation. after the "15h"or"10h" command, the result per plane of the operation is show n through the "78h" multi plane read status command. 0g figure 44. multi pl ane cache program notes: 1. plane 0 and plane 1 should be selected within the same chip 2. only one block should be selected from the each plane. 3. multi plane cache program is available only within a block per plane. 4. selected page address except for a22 within two blocks must be same. 5. the operation has to be terminated with ?10h? command.? 6. any command between 11h and 81h is prohibited except 70h/78h and ffh. 7. read status command can be 70h or 78h. re ading the status per plan e is available only 78h. 4.11. g copy-back program copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit er ror is not in data stored. since the time-consuming re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a po rtion of a block is updated and the rest of the block needs to be co pied to the newly assigned free block. copy-back oper ation is a sequential exe- cution of read for copy-back and of copy-back program wi th the destination page addr ess. a read operation with "35h" command and the address of the source page moves th e whole 8,640-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore, copy-back program operation is initiated by issuing page-copy data-input command (85h) 80h t cbsyw a 80h 81h i/ox r/b# a address (5 cycle) data input 11h address (5 cycle) data input 11h 81h address (5 cycle) data input 15h t dbsy address (5 cycle) data input 10h 78h address (3 cycle) status per plane column address : valid page address : page m plane address : fixed low block address : block j column address : valid page address : page m plane address : fixed high block address : block k column address : valid page address : page m+n plane address : fixed low block address : block j column address : valid page address : page m+n plane address : fixed high block address : block k i/ox r/b# t prog t dbsy 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 47 with destination page address. actual programming operat ion begins after program conf irm command (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controller can detect the completion of a progra m cycle by monitoring the r/b# output, or the status bit (i/o 6) of the status register. when the copy-back program is complete, the write status bit (i/o 0) may be checked. the command register remains in read status command mo de until another valid command is written to the com- mand register. during copy-back progra m, data modification is possible usin g random data input command (85h) as shown in figure 45. 0 figure 45. copyback program 4.12. g multi plane copy-back program multi plane copy-back program is an extension of copy-back program, for a single plane with 8,640 byte page regis- ters. since the device is equipped with two memory plan es, activating the two sets of 8,640-byte page registers enables a simultaneous programming of two pages. figure 46 and figure 47 show command sequence for the multi plane copy-back operation. first case, figure 46, shows random data input of two planes th at started right after finish- ing random data output of previous two planes. second ca se, figure 47, shows the random data input of each plane which started right after finishing the random data output of each plane. 00h address (5 cycle) 35h data output t r 85h address (5 cycle) data t prog i/ox r/b# target address 85h address (2 cycle) data 10h 70h status column address 1,2 i/ox r/b# source address a a 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 48 0 figure 46. multi plane copyback program 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : valid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : valid page address : page n plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data 11h i/ox r/b# d column address 1,2 : valid 81h address (5 cycle) data 10h data 85h address (2 cycle) 85h data t prog i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) 05h e0h data output column address : valid page address : page n plane address : fixed high block address : block q t dbsy 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 49 0 figure 47. multi plane copyback program 4.13. g block erase the erase operation is done on a block basis. block address lo ading is accomplished in two cycles initiated by an erase setup command (60h). only address a22 to a31 is valid while a14 to a21 is ignored. the erase confirm command (d0h) following the block addres s loading initiates the internal erasing proc ess. this two-step sequence of setup fol- lowed by execution command en sures that memory contents are not accident ally erased due to external noise condi- tions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase verify. once the erase process starts, the read status register co mmand may be entered to read the status register. the sys- 60h t r a i/ox r/b# a address (3 cycle) page address : page m plane address : fixed low block address : block j column address : fixed low page address : page m plane address : fixed low block address : block j column address 1,2 : valid address (3 cycle) 60h 35h page address : page m plane address : fixed high block address : block k b i/ox r/b# 00h address (5 cycle) address (2 cycle) 05h e0h data output i/ox r/b# b column address : valid page address : page n plane address : fixed low block address : block p column address 1,2 : valid c 85h address (5 cycle) address (2 cycle) data data i/ox r/b# c column address : fixed low page address : page m plane address : fixed high block address : block k column address 1,2 : valid d 00h address (5 cycle) address (2 cycle) i/ox r/b# d column address : valid page address : page n plane address : fixed high block address : block q column address 1,2 : valid 81h address (5 cycle) data 10h e0h 05h address (2 cycle) 85h data t prog 85h 11h t dbsy data output 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 50 tem controller can detect the completion of an erase by monitoring the r/b# outp ut, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 48 details the sequence. 0 figure 48. block erase 4.14. g multi plane block erase multiple plane erase, allows parallel eras e of two blocks, one per each memory plane. block erase setup command (60h) must be repeated two time s, each time followed by first block and second block address respectively (3 cycles each). as for block erase, d0h command makes embedded operation start. multi plane erase does not need any dummy busy time between first and second block address inse rtion. address limitation required for multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for multiple plane program. refer to the detail sequence as shown below. 0 figure 49. multi plane block erase 4.15. g reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next co mmand, and the status register is cleared to value e0h when wp# is high. refer to 2.8. status register coding for device status after reset operatio n. if the device is already in reset state, the command reg- ister will not accept a new reset co mmand. the r/b# pin goes low for t rst after the reset command is written. refer to figure 50. 60h 70h address (3 cycle) d0h status t bers i/ox r/b# row add 1,2,3 60h 70h address (3 cycle) 60h status t bers address (3 cycle) d0h page address : fixed low plane address : fixed low block address : block n i/ox r/b# page address : fixed low plane address : fixed high block address : block m 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 51 0 figure 50. reset i/ox r/b# ffh rst t 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 52 5. g interleaved operation interleaving operations improve the system throughput co mpared to non-interleaving operations. in the stacked device sharing a common ce# pin, interleaved operation is available. when both chip are ready state, input a com- mand to the chip #1. and then, while chip #1 is busy st ate, issue a command to the other chip. when performing interleaved operations, the operations shall be the same type . the functions that may be used in the interleaved oper- ations are page read, page program, block erase, multi pl ane page read, multi plane page program, and multi plane block erase. during interleaved operations, 70h command is pr ohibited exceptionally. each chip status can be checked by multi plane read status command (78h). the r/b# pin shows when both chip are ready or busy. while either chip is busy, r/b# pin is low. all chips are ready state and inte rleaved operations are complete , r/b# pin goes high. cache function and copyback function are impossible for interleaved operation. 5.1. interleaved page read figure 51 shows how to perfor m interleaved page read operations. in figu re, the status register is monitored for operation completion with the multi plane status read ( 78h) command. when the host has issued page read com- mands to multiple die at the same time, the host shall i ssue multi plane status read (78h) command before reading data from either die. this ensures that only the die selected by the 78h comman d responds to a data output cycle after being put in data output mode with a 00h command, and thus avoiding bus contention. the host can use 78h com- mands to read out data from another die. 0 figure 51. interleaved page read note: 70h command is prohibited during interleaved operations. 5.2. interleaved mu lti plane page read figure 52 shows how to perform interleaved multi plane page read operations using the multi plane read status (78h) command to monitor the status register for operation comp letion. when the host has is sued multi plane page read commands to multiple die at the same ti me, the host shall issue multi plane read status (78h) command before read- ing data from either die. this ensures that only the die se lected by the 78h command resp onds to a data output cycle after being put in data output mode with a 00h command and 5 address cycles, and thus avoiding bus contention. the interleaved multi plane page read operation mu st meet two-plane addressing requirements. data out 00h status row. add3 78h row. add2 row. add1 00h 30h 00h 30h address (5cycle) address (5cycle) 00h status row. add3 78h row. add2 row. add1 data out chip 2 chip 1 chip 1 chip 1 chip 2 chip 2 i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 53 0 figure 52. interleaved multi plane page read note: 70h command is prohibited during interleaved operations. 5.3. interleaved page program figure 53 show how to perform interleaved program page operations. random data input (85h) is permitted during interleaved program page operations. 0 figure 53. interleaved page program note: 70h command is prohibited during interleaved operations. 5.4. interleaved mult i plane page program figure 54 shows how to perform interl eaved multi plane page program operations. the interleaved two-plane pro- gram page operation must meet two-pl ane addressing requirements. random data input (85h) is permitted during interleaved multi plane page program operation. a 00h address (5cycle) 78h row add.1 row add.2 row add.3 status 05h address (2cycle) e0h chip 2 05h address (2cycle) e0h 00h address (5cycle) data output chip 2. plane 0 chip 2. plane 0 chip 2. plane 1 data output 00h address (5cycle) 05h address (2cycle) e0h data output chip 1. plane 0 chip 1. plane 0 chip 2. plane 1 a 60h 60h 60h 60h 30h 78h 00h 05h e0h address (3cycle) address (5cycle) 30h address (3cycle) address (3cycle) row add.1 row add.2 row add.3 status address (5cycle) address (2cycle) data output chip 1 chip 1 chip 2 chip 2 chip 1 chip 1, plane 0 chip 1, plane 0 chip 1, plane 0 i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) i/ox r/b# (chip 1 internal) r/b# (chip 2 internal) r/b# (external) r/b# (chip 1 internal) i/ox 80h address (5cycle) data input 10h 80h address (5cycle) data input 10h row add.1 row add.2 row add.3 status 80h address (5cycle) data input 10h chip 1 chip 2 chip 1 chip 1 r/b# (chip 2 internal) r/b# (external) 78h 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 54 0 figure 54. interleaved mu lti plane page program note: 70h command is prohibited during interleaved operations. 5.5. interleaved block erase figure 55 shows how to perform in terleaved block erase operation. 0 figure 55. interleaved block erase note: 70h command is prohibited during interleaved operations. r/b# (chip 1 internal) i/ox r/b# (chip 2 internal) r/b# (external) r/b# (chip 1 internal) i/ox r/b# (chip 2 internal) r/b# (external) a a row. add.1 row. add.2 row. add.3 78h 80h status address. (5cycle) data input 11h 81h address. (5cycle) data input 10h 80h address. (5cycle) data input 11h 81h address. (5cycle) data input 10h 80h address. (5cycle) data input 11h 81h address. (5cycle) data input 10h chip 1 chip 1 chip 2 chip 2 chip 1 chip 1 chip 1 r/b# (chip 1 internal) i/ox 60h chip 1 chip 2 chip 1 r/b# (chip 2 internal) r/b# (external) address (3cycle) d0h 60h address (3cycle) d0h 60h address (3cycle) d0h 60h address (3cycle) d0h chip 2 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 55 5.6. interleaved multi plane block erase figure 56 shows how to perform two types of interleaved mu lti plane block erase operations . this operation must meet two-plane addressing requirements. 0 figure 56. interleaved multi plane block erase note: 70h command is prohibited during interleaved operations. r/b# (chip 1 internal) i/ox 60h chip 1 chip 1 chip 2 r/b# (chip 2 internal) r/b# (external) address (3cycle) 60h address (3cycle) d0h chip 2 60h address (3cycle) 60h address (3cycle) d0h 78h row. add 1. 60h address (3cycle) 60h address (3cycle) d0h row. add 2. row. add. 3 status chip 1 chip 1 chip 1 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 56 6. other features 6.1. data protection & power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions whenever v cc is below about 2.0v (3.3v device). wp# pin provides hardware protection and is recommended to be kept at vil during powe r-up and power-down. the reset command (ffh) must be issued to all dies as the first command after device is power up. each r/b# will be busy for maximum of 2ms after reset command is issued. in this time, the acceptable command is 70h or 78h. 0 figure 57. data protecti on and power on / off 6.2. ready / busy the device has a ready/busy output that provides method of indicating the completion of a page program, erase, copy-back and random read completion. the r/b# pin is normally high and goes to low when the device is busy (after a reset, read, program, and erase operation). it returns to hi gh when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or mo re r/b# outputs to be or-tied. because pull-up resistor value is related to tr (r/b#) and curren t drain during busy (ibusy), an appropri ate value can be obtained with the fol- lowing reference chart (figure 58). its value can be determined by the following guidance. 3v device = 2.7v t cs ffh 2.7v 1 (max) ms 10 (max) 50 (min) 2 (max) ms vcc ramp starts : dont care : undefined vcc 0v ce# wp# cle we# ale re# i/ox r/b# 58b7d520e522 ivuuuvwwtwtwa
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 57 0 figure 58. ready / busy rp value guidence rp (min) = = where il is the sum of the input current of all devices tied to the r/b# pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3v, ta = 25c, c l =50pf fig. rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 3.2v p$?, l i ol + ?, l rp ibusy rp (ohm) ibusy ibusy [a] tr, tf [s] tf 3.3 381 290 1.65 96 189 1.1 0.825 4.2 4.2 4.2 4.2 busy ready vcc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 300n 3m 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b# 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 58 6.3. write prot ect operation the erase and program operations are automatically rese t when wp# goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 59 ~ 62). figure 59. enable programming figure 60. disable programming figure 61. enable erasing figure 62. disable erasing 80h 10h we# i/ox wp# r/b# ww t 80h 10h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 60h d0h we# i/ox wp# r/b# ww t 58b7d520-e522 iyvuuuyyvywwtwtwgaz
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 59 7. application notes and comments 7.1. paired page address information paired page address paired page address 0415 2839 6c7d a10b11 e14f15 12 18 13 19 16 1c 17 1d 1a 20 1b 21 1e 24 1f 25 22 28 23 29 26 2c 27 2d 2a 30 2b 31 2e 34 2f 35 32 38 33 39 36 3c 37 3d 3a 40 3b 41 3e 44 3f 45 42 48 43 49 46 4c 47 4d 4a 50 4b 51 4e 54 4f 55 52 58 53 59 56 5c 57 5d 5a 60 5b 61 5e 64 5f 65 62 68 63 69 66 6c 67 6d 6a 70 6b 71 6e 74 6f 75 72 78 73 79 76 7c 77 7d 7a 80 7b 81 7e 84 7f 85 82 88 83 89 86 8c 87 8d 8a 90 8b 91 8e 94 8f 95 92 98 93 99 96 9c 97 9d 9a a0 9b a1 9e a4 9f a5 a2 a8 a3 a9 a6 ac a7 ad aa b0 ab b1 ae b4 af b5 b2 b8 b3 b9 b6 bc b7 bd ba c0 bb c1 be c4 bf c5 c2 c8 c3 c9 c6 cc c7 cd ca d0 cb d1 ce d4 cf d5 *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 60 when program operation is abnormally aborted (ex. power-do wn, reset), not only page data under program but also a coupled row paired page data may be damaged. for example, during page program operation of page address 05h is aborted by reset or power down, the data of 00h , 01h, 04h, and 05h page address may be spoiled. 7.2. extra block description device includes extra features like user otp, unique id and read id2. user otp, unique id can be programmed only once and cannot be erased. the user otp used one block which locates the second block of plane 0 (address<31:22> = 0002h). unique id block has 64 pages, locates the firs t block of plane 0 and the fi rst 64 pages of the block (address<32:22> = 0000h, address<21:14> = 00h ~ 3fh). read id2 can be only read, the size is one page. physi- cally, readid2 area exists in plane1, but user block address do es not care internally. to exit extra features, 07h or ffh command can be used. 7.3. acceptable command after 80h after program start command (80h) is inpu tted, do not input any command except 85h, 10h, 11h, 15h, and ffh. if a command is inputted except these commands, the program operation cannot be executed. 7.4. acceptable command between start command an d confirm command only reset command is available between start comman ds and confirm commands set (start command-address-con- firm command style) that is mentioned in 1.7 command set. if other command is inputted, the operation cannot be executed. do not input any commands exce pt ffh. for instance, it is impossible to perform a normal page read oper- ation, if any command is inputted between page read command set (00h - 5 address cycle - 30h). 7.5. restriction of read status value in multi plane operation during multi plane operation, only 70h, 78h, and ffh are av ailable between 11h-81h. but, the pass/fail output informa- tion of 70h and 78h is not valid. during this time, only ready / busy (i/o6 and i/o5) state can be checked. refer to fig- ure 63. d2 d8 d3 d9 d6 dc d7 dd da e0 db e1 de e4 df e5 e2 e8 e3 e9 e6 ec e7 ed ea f0 eb f1 ee f4 ef f5 f2 f8 f3 f9 f6 fc f7 fd fa fe fb ff *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`
a pcpcwm_4828539:wp_0000001wp_0000001 apcpcwm_4828539:wp_0000001wp_0000001 release H27UAG8T2B series 16gb (2048m x 8bit) nand flash rev 1.0 / aug. 2010 61 figure 63. restriction read status in multi plane operation 7.6. page program failure if the page program operation for page address n is fail, remain data in data register may be different to input data by host. therefore, do not attempt to program the page addre ss n in another block without the data input sequence. the same input sequence of 80h command, address and data is necessary. 7.7. restriction multi plane operation to prevent abnormal multi plane operatio n, do not input bad block address to al l multi plane operation. otherwise, the input data of valid block could be lost an d the operation could be abnormally stopped. 80h i/ox r/b# address data i/o6 => i/o5 => i/o1 => i/o0 => valid invalid invalid invalid 11h 70h sr out 81h address data 10h 70h sr out valid invalid invalid invalid valid invalid invalid valid 70h sr out t prog t dbsy io 0 = 0, pass io 0 = 1, fail *58b7d520-e522* iy]^`_vx^^ux^`ux\^uyxyvywxwtw_tw]gx^az`

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